
eight-queen:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004004f8 <_init>:
  4004f8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4004fc:	910003fd 	mov	x29, sp
  400500:	94000036 	bl	4005d8 <call_weak_fn>
  400504:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400508:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400510 <.plt>:
  400510:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400514:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf2f0>
  400518:	f947fe11 	ldr	x17, [x16, #4088]
  40051c:	913fe210 	add	x16, x16, #0xff8
  400520:	d61f0220 	br	x17
  400524:	d503201f 	nop
  400528:	d503201f 	nop
  40052c:	d503201f 	nop

0000000000400530 <__libc_start_main@plt>:
  400530:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400534:	f9400211 	ldr	x17, [x16]
  400538:	91000210 	add	x16, x16, #0x0
  40053c:	d61f0220 	br	x17

0000000000400540 <memset@plt>:
  400540:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400544:	f9400611 	ldr	x17, [x16, #8]
  400548:	91002210 	add	x16, x16, #0x8
  40054c:	d61f0220 	br	x17

0000000000400550 <__gmon_start__@plt>:
  400550:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400554:	f9400a11 	ldr	x17, [x16, #16]
  400558:	91004210 	add	x16, x16, #0x10
  40055c:	d61f0220 	br	x17

0000000000400560 <abort@plt>:
  400560:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400564:	f9400e11 	ldr	x17, [x16, #24]
  400568:	91006210 	add	x16, x16, #0x18
  40056c:	d61f0220 	br	x17

0000000000400570 <printf@plt>:
  400570:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400574:	f9401211 	ldr	x17, [x16, #32]
  400578:	91008210 	add	x16, x16, #0x20
  40057c:	d61f0220 	br	x17

0000000000400580 <putchar@plt>:
  400580:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400584:	f9401611 	ldr	x17, [x16, #40]
  400588:	9100a210 	add	x16, x16, #0x28
  40058c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400590 <_start>:
  400590:	d280001d 	mov	x29, #0x0                   	// #0
  400594:	d280001e 	mov	x30, #0x0                   	// #0
  400598:	aa0003e5 	mov	x5, x0
  40059c:	f94003e1 	ldr	x1, [sp]
  4005a0:	910023e2 	add	x2, sp, #0x8
  4005a4:	910003e6 	mov	x6, sp
  4005a8:	580000c0 	ldr	x0, 4005c0 <_start+0x30>
  4005ac:	580000e3 	ldr	x3, 4005c8 <_start+0x38>
  4005b0:	58000104 	ldr	x4, 4005d0 <_start+0x40>
  4005b4:	97ffffdf 	bl	400530 <__libc_start_main@plt>
  4005b8:	97ffffea 	bl	400560 <abort@plt>
  4005bc:	00000000 	.inst	0x00000000 ; undefined
  4005c0:	00400bb4 	.word	0x00400bb4
  4005c4:	00000000 	.word	0x00000000
  4005c8:	00400bf0 	.word	0x00400bf0
  4005cc:	00000000 	.word	0x00000000
  4005d0:	00400c70 	.word	0x00400c70
  4005d4:	00000000 	.word	0x00000000

00000000004005d8 <call_weak_fn>:
  4005d8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf2f0>
  4005dc:	f947f000 	ldr	x0, [x0, #4064]
  4005e0:	b4000040 	cbz	x0, 4005e8 <call_weak_fn+0x10>
  4005e4:	17ffffdb 	b	400550 <__gmon_start__@plt>
  4005e8:	d65f03c0 	ret
  4005ec:	00000000 	.inst	0x00000000 ; undefined

00000000004005f0 <deregister_tm_clones>:
  4005f0:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  4005f4:	91010000 	add	x0, x0, #0x40
  4005f8:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  4005fc:	91010021 	add	x1, x1, #0x40
  400600:	eb00003f 	cmp	x1, x0
  400604:	540000a0 	b.eq	400618 <deregister_tm_clones+0x28>  // b.none
  400608:	90000001 	adrp	x1, 400000 <_init-0x4f8>
  40060c:	f9464821 	ldr	x1, [x1, #3216]
  400610:	b4000041 	cbz	x1, 400618 <deregister_tm_clones+0x28>
  400614:	d61f0020 	br	x1
  400618:	d65f03c0 	ret
  40061c:	d503201f 	nop

0000000000400620 <register_tm_clones>:
  400620:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400624:	91010000 	add	x0, x0, #0x40
  400628:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40062c:	91010021 	add	x1, x1, #0x40
  400630:	cb000021 	sub	x1, x1, x0
  400634:	9343fc21 	asr	x1, x1, #3
  400638:	8b41fc21 	add	x1, x1, x1, lsr #63
  40063c:	9341fc21 	asr	x1, x1, #1
  400640:	b40000a1 	cbz	x1, 400654 <register_tm_clones+0x34>
  400644:	90000002 	adrp	x2, 400000 <_init-0x4f8>
  400648:	f9464c42 	ldr	x2, [x2, #3224]
  40064c:	b4000042 	cbz	x2, 400654 <register_tm_clones+0x34>
  400650:	d61f0040 	br	x2
  400654:	d65f03c0 	ret

0000000000400658 <__do_global_dtors_aux>:
  400658:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40065c:	910003fd 	mov	x29, sp
  400660:	f9000bf3 	str	x19, [sp, #16]
  400664:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  400668:	39410260 	ldrb	w0, [x19, #64]
  40066c:	35000080 	cbnz	w0, 40067c <__do_global_dtors_aux+0x24>
  400670:	97ffffe0 	bl	4005f0 <deregister_tm_clones>
  400674:	52800020 	mov	w0, #0x1                   	// #1
  400678:	39010260 	strb	w0, [x19, #64]
  40067c:	f9400bf3 	ldr	x19, [sp, #16]
  400680:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400684:	d65f03c0 	ret

0000000000400688 <frame_dummy>:
  400688:	17ffffe6 	b	400620 <register_tm_clones>

000000000040068c <not_danger>:
  40068c:	d100c3ff 	sub	sp, sp, #0x30
  400690:	b9000fe0 	str	w0, [sp, #12]
  400694:	b9000be1 	str	w1, [sp, #8]
  400698:	f90003e2 	str	x2, [sp]
  40069c:	b90017ff 	str	wzr, [sp, #20]
  4006a0:	b94017e0 	ldr	w0, [sp, #20]
  4006a4:	b9001be0 	str	w0, [sp, #24]
  4006a8:	b9401be0 	ldr	w0, [sp, #24]
  4006ac:	b9001fe0 	str	w0, [sp, #28]
  4006b0:	b9401fe0 	ldr	w0, [sp, #28]
  4006b4:	b90023e0 	str	w0, [sp, #32]
  4006b8:	b94023e0 	ldr	w0, [sp, #32]
  4006bc:	b90027e0 	str	w0, [sp, #36]
  4006c0:	b9002fff 	str	wzr, [sp, #44]
  4006c4:	14000011 	b	400708 <not_danger+0x7c>
  4006c8:	b9802fe0 	ldrsw	x0, [sp, #44]
  4006cc:	d37be800 	lsl	x0, x0, #5
  4006d0:	f94003e1 	ldr	x1, [sp]
  4006d4:	8b000021 	add	x1, x1, x0
  4006d8:	b9800be0 	ldrsw	x0, [sp, #8]
  4006dc:	d37ef400 	lsl	x0, x0, #2
  4006e0:	8b000020 	add	x0, x1, x0
  4006e4:	b9400000 	ldr	w0, [x0]
  4006e8:	7100001f 	cmp	w0, #0x0
  4006ec:	54000080 	b.eq	4006fc <not_danger+0x70>  // b.none
  4006f0:	52800020 	mov	w0, #0x1                   	// #1
  4006f4:	b90027e0 	str	w0, [sp, #36]
  4006f8:	14000007 	b	400714 <not_danger+0x88>
  4006fc:	b9402fe0 	ldr	w0, [sp, #44]
  400700:	11000400 	add	w0, w0, #0x1
  400704:	b9002fe0 	str	w0, [sp, #44]
  400708:	b9402fe0 	ldr	w0, [sp, #44]
  40070c:	71001c1f 	cmp	w0, #0x7
  400710:	54fffdcd 	b.le	4006c8 <not_danger+0x3c>
  400714:	b9400fe0 	ldr	w0, [sp, #12]
  400718:	b9002fe0 	str	w0, [sp, #44]
  40071c:	b9400be0 	ldr	w0, [sp, #8]
  400720:	b9002be0 	str	w0, [sp, #40]
  400724:	14000014 	b	400774 <not_danger+0xe8>
  400728:	b9802fe0 	ldrsw	x0, [sp, #44]
  40072c:	d37be800 	lsl	x0, x0, #5
  400730:	f94003e1 	ldr	x1, [sp]
  400734:	8b000021 	add	x1, x1, x0
  400738:	b9802be0 	ldrsw	x0, [sp, #40]
  40073c:	d37ef400 	lsl	x0, x0, #2
  400740:	8b000020 	add	x0, x1, x0
  400744:	b9400000 	ldr	w0, [x0]
  400748:	7100001f 	cmp	w0, #0x0
  40074c:	54000080 	b.eq	40075c <not_danger+0xd0>  // b.none
  400750:	52800020 	mov	w0, #0x1                   	// #1
  400754:	b90023e0 	str	w0, [sp, #32]
  400758:	1400000d 	b	40078c <not_danger+0x100>
  40075c:	b9402fe0 	ldr	w0, [sp, #44]
  400760:	51000400 	sub	w0, w0, #0x1
  400764:	b9002fe0 	str	w0, [sp, #44]
  400768:	b9402be0 	ldr	w0, [sp, #40]
  40076c:	51000400 	sub	w0, w0, #0x1
  400770:	b9002be0 	str	w0, [sp, #40]
  400774:	b9402fe0 	ldr	w0, [sp, #44]
  400778:	7100001f 	cmp	w0, #0x0
  40077c:	5400008b 	b.lt	40078c <not_danger+0x100>  // b.tstop
  400780:	b9402be0 	ldr	w0, [sp, #40]
  400784:	7100001f 	cmp	w0, #0x0
  400788:	54fffd0a 	b.ge	400728 <not_danger+0x9c>  // b.tcont
  40078c:	b9400fe0 	ldr	w0, [sp, #12]
  400790:	b9002fe0 	str	w0, [sp, #44]
  400794:	b9400be0 	ldr	w0, [sp, #8]
  400798:	b9002be0 	str	w0, [sp, #40]
  40079c:	14000014 	b	4007ec <not_danger+0x160>
  4007a0:	b9802fe0 	ldrsw	x0, [sp, #44]
  4007a4:	d37be800 	lsl	x0, x0, #5
  4007a8:	f94003e1 	ldr	x1, [sp]
  4007ac:	8b000021 	add	x1, x1, x0
  4007b0:	b9802be0 	ldrsw	x0, [sp, #40]
  4007b4:	d37ef400 	lsl	x0, x0, #2
  4007b8:	8b000020 	add	x0, x1, x0
  4007bc:	b9400000 	ldr	w0, [x0]
  4007c0:	7100001f 	cmp	w0, #0x0
  4007c4:	54000080 	b.eq	4007d4 <not_danger+0x148>  // b.none
  4007c8:	52800020 	mov	w0, #0x1                   	// #1
  4007cc:	b9001fe0 	str	w0, [sp, #28]
  4007d0:	1400000d 	b	400804 <not_danger+0x178>
  4007d4:	b9402fe0 	ldr	w0, [sp, #44]
  4007d8:	11000400 	add	w0, w0, #0x1
  4007dc:	b9002fe0 	str	w0, [sp, #44]
  4007e0:	b9402be0 	ldr	w0, [sp, #40]
  4007e4:	11000400 	add	w0, w0, #0x1
  4007e8:	b9002be0 	str	w0, [sp, #40]
  4007ec:	b9402fe0 	ldr	w0, [sp, #44]
  4007f0:	71001c1f 	cmp	w0, #0x7
  4007f4:	5400008c 	b.gt	400804 <not_danger+0x178>
  4007f8:	b9402be0 	ldr	w0, [sp, #40]
  4007fc:	71001c1f 	cmp	w0, #0x7
  400800:	54fffd0d 	b.le	4007a0 <not_danger+0x114>
  400804:	b9400fe0 	ldr	w0, [sp, #12]
  400808:	b9002fe0 	str	w0, [sp, #44]
  40080c:	b9400be0 	ldr	w0, [sp, #8]
  400810:	b9002be0 	str	w0, [sp, #40]
  400814:	14000014 	b	400864 <not_danger+0x1d8>
  400818:	b9802fe0 	ldrsw	x0, [sp, #44]
  40081c:	d37be800 	lsl	x0, x0, #5
  400820:	f94003e1 	ldr	x1, [sp]
  400824:	8b000021 	add	x1, x1, x0
  400828:	b9802be0 	ldrsw	x0, [sp, #40]
  40082c:	d37ef400 	lsl	x0, x0, #2
  400830:	8b000020 	add	x0, x1, x0
  400834:	b9400000 	ldr	w0, [x0]
  400838:	7100001f 	cmp	w0, #0x0
  40083c:	54000080 	b.eq	40084c <not_danger+0x1c0>  // b.none
  400840:	52800020 	mov	w0, #0x1                   	// #1
  400844:	b9001be0 	str	w0, [sp, #24]
  400848:	1400000d 	b	40087c <not_danger+0x1f0>
  40084c:	b9402fe0 	ldr	w0, [sp, #44]
  400850:	51000400 	sub	w0, w0, #0x1
  400854:	b9002fe0 	str	w0, [sp, #44]
  400858:	b9402be0 	ldr	w0, [sp, #40]
  40085c:	11000400 	add	w0, w0, #0x1
  400860:	b9002be0 	str	w0, [sp, #40]
  400864:	b9402fe0 	ldr	w0, [sp, #44]
  400868:	7100001f 	cmp	w0, #0x0
  40086c:	5400008b 	b.lt	40087c <not_danger+0x1f0>  // b.tstop
  400870:	b9402be0 	ldr	w0, [sp, #40]
  400874:	71001c1f 	cmp	w0, #0x7
  400878:	54fffd0d 	b.le	400818 <not_danger+0x18c>
  40087c:	b9400fe0 	ldr	w0, [sp, #12]
  400880:	b9002fe0 	str	w0, [sp, #44]
  400884:	b9400be0 	ldr	w0, [sp, #8]
  400888:	b9002be0 	str	w0, [sp, #40]
  40088c:	14000014 	b	4008dc <not_danger+0x250>
  400890:	b9802fe0 	ldrsw	x0, [sp, #44]
  400894:	d37be800 	lsl	x0, x0, #5
  400898:	f94003e1 	ldr	x1, [sp]
  40089c:	8b000021 	add	x1, x1, x0
  4008a0:	b9802be0 	ldrsw	x0, [sp, #40]
  4008a4:	d37ef400 	lsl	x0, x0, #2
  4008a8:	8b000020 	add	x0, x1, x0
  4008ac:	b9400000 	ldr	w0, [x0]
  4008b0:	7100001f 	cmp	w0, #0x0
  4008b4:	54000080 	b.eq	4008c4 <not_danger+0x238>  // b.none
  4008b8:	52800020 	mov	w0, #0x1                   	// #1
  4008bc:	b90017e0 	str	w0, [sp, #20]
  4008c0:	1400000d 	b	4008f4 <not_danger+0x268>
  4008c4:	b9402fe0 	ldr	w0, [sp, #44]
  4008c8:	11000400 	add	w0, w0, #0x1
  4008cc:	b9002fe0 	str	w0, [sp, #44]
  4008d0:	b9402be0 	ldr	w0, [sp, #40]
  4008d4:	51000400 	sub	w0, w0, #0x1
  4008d8:	b9002be0 	str	w0, [sp, #40]
  4008dc:	b9402fe0 	ldr	w0, [sp, #44]
  4008e0:	71001c1f 	cmp	w0, #0x7
  4008e4:	5400008c 	b.gt	4008f4 <not_danger+0x268>
  4008e8:	b9402be0 	ldr	w0, [sp, #40]
  4008ec:	7100001f 	cmp	w0, #0x0
  4008f0:	54fffd0a 	b.ge	400890 <not_danger+0x204>  // b.tcont
  4008f4:	b94027e0 	ldr	w0, [sp, #36]
  4008f8:	7100001f 	cmp	w0, #0x0
  4008fc:	540001a1 	b.ne	400930 <not_danger+0x2a4>  // b.any
  400900:	b94023e0 	ldr	w0, [sp, #32]
  400904:	7100001f 	cmp	w0, #0x0
  400908:	54000141 	b.ne	400930 <not_danger+0x2a4>  // b.any
  40090c:	b9401fe0 	ldr	w0, [sp, #28]
  400910:	7100001f 	cmp	w0, #0x0
  400914:	540000e1 	b.ne	400930 <not_danger+0x2a4>  // b.any
  400918:	b9401be0 	ldr	w0, [sp, #24]
  40091c:	7100001f 	cmp	w0, #0x0
  400920:	54000081 	b.ne	400930 <not_danger+0x2a4>  // b.any
  400924:	b94017e0 	ldr	w0, [sp, #20]
  400928:	7100001f 	cmp	w0, #0x0
  40092c:	54000060 	b.eq	400938 <not_danger+0x2ac>  // b.none
  400930:	52800000 	mov	w0, #0x0                   	// #0
  400934:	14000002 	b	40093c <not_danger+0x2b0>
  400938:	52800020 	mov	w0, #0x1                   	// #1
  40093c:	9100c3ff 	add	sp, sp, #0x30
  400940:	d65f03c0 	ret

0000000000400944 <eight_queen>:
  400944:	a9ad7bfd 	stp	x29, x30, [sp, #-304]!
  400948:	910003fd 	mov	x29, sp
  40094c:	b9001fa0 	str	w0, [x29, #28]
  400950:	b9001ba1 	str	w1, [x29, #24]
  400954:	f9000ba2 	str	x2, [x29, #16]
  400958:	b9012fbf 	str	wzr, [x29, #300]
  40095c:	14000019 	b	4009c0 <eight_queen+0x7c>
  400960:	b9012bbf 	str	wzr, [x29, #296]
  400964:	14000011 	b	4009a8 <eight_queen+0x64>
  400968:	b9812fa0 	ldrsw	x0, [x29, #300]
  40096c:	d37be800 	lsl	x0, x0, #5
  400970:	f9400ba1 	ldr	x1, [x29, #16]
  400974:	8b000020 	add	x0, x1, x0
  400978:	b9812ba1 	ldrsw	x1, [x29, #296]
  40097c:	b8617802 	ldr	w2, [x0, x1, lsl #2]
  400980:	b9812ba0 	ldrsw	x0, [x29, #296]
  400984:	b9812fa1 	ldrsw	x1, [x29, #300]
  400988:	d37df021 	lsl	x1, x1, #3
  40098c:	8b000020 	add	x0, x1, x0
  400990:	d37ef400 	lsl	x0, x0, #2
  400994:	9100a3a1 	add	x1, x29, #0x28
  400998:	b8206822 	str	w2, [x1, x0]
  40099c:	b9412ba0 	ldr	w0, [x29, #296]
  4009a0:	11000400 	add	w0, w0, #0x1
  4009a4:	b9012ba0 	str	w0, [x29, #296]
  4009a8:	b9412ba0 	ldr	w0, [x29, #296]
  4009ac:	71001c1f 	cmp	w0, #0x7
  4009b0:	54fffdcd 	b.le	400968 <eight_queen+0x24>
  4009b4:	b9412fa0 	ldr	w0, [x29, #300]
  4009b8:	11000400 	add	w0, w0, #0x1
  4009bc:	b9012fa0 	str	w0, [x29, #300]
  4009c0:	b9412fa0 	ldr	w0, [x29, #300]
  4009c4:	71001c1f 	cmp	w0, #0x7
  4009c8:	54fffccd 	b.le	400960 <eight_queen+0x1c>
  4009cc:	b9401fa1 	ldr	w1, [x29, #28]
  4009d0:	910073a2 	add	x2, x29, #0x1c
  4009d4:	90000000 	adrp	x0, 400000 <_init-0x4f8>
  4009d8:	91328000 	add	x0, x0, #0xca0
  4009dc:	97fffee5 	bl	400570 <printf@plt>
  4009e0:	b9401fa0 	ldr	w0, [x29, #28]
  4009e4:	7100201f 	cmp	w0, #0x8
  4009e8:	540005e1 	b.ne	400aa4 <eight_queen+0x160>  // b.any
  4009ec:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  4009f0:	91011000 	add	x0, x0, #0x44
  4009f4:	b9400000 	ldr	w0, [x0]
  4009f8:	11000401 	add	w1, w0, #0x1
  4009fc:	90000000 	adrp	x0, 400000 <_init-0x4f8>
  400a00:	91330000 	add	x0, x0, #0xcc0
  400a04:	97fffedb 	bl	400570 <printf@plt>
  400a08:	b9012fbf 	str	wzr, [x29, #300]
  400a0c:	14000019 	b	400a70 <eight_queen+0x12c>
  400a10:	b9012bbf 	str	wzr, [x29, #296]
  400a14:	1400000f 	b	400a50 <eight_queen+0x10c>
  400a18:	b9812fa0 	ldrsw	x0, [x29, #300]
  400a1c:	d37df001 	lsl	x1, x0, #3
  400a20:	b9812ba0 	ldrsw	x0, [x29, #296]
  400a24:	8b000020 	add	x0, x1, x0
  400a28:	d37ef400 	lsl	x0, x0, #2
  400a2c:	9100a3a1 	add	x1, x29, #0x28
  400a30:	8b000020 	add	x0, x1, x0
  400a34:	b9400001 	ldr	w1, [x0]
  400a38:	90000000 	adrp	x0, 400000 <_init-0x4f8>
  400a3c:	91334000 	add	x0, x0, #0xcd0
  400a40:	97fffecc 	bl	400570 <printf@plt>
  400a44:	b9412ba0 	ldr	w0, [x29, #296]
  400a48:	11000400 	add	w0, w0, #0x1
  400a4c:	b9012ba0 	str	w0, [x29, #296]
  400a50:	b9412ba0 	ldr	w0, [x29, #296]
  400a54:	71001c1f 	cmp	w0, #0x7
  400a58:	54fffe0d 	b.le	400a18 <eight_queen+0xd4>
  400a5c:	52800140 	mov	w0, #0xa                   	// #10
  400a60:	97fffec8 	bl	400580 <putchar@plt>
  400a64:	b9412fa0 	ldr	w0, [x29, #300]
  400a68:	11000400 	add	w0, w0, #0x1
  400a6c:	b9012fa0 	str	w0, [x29, #300]
  400a70:	b9412fa0 	ldr	w0, [x29, #300]
  400a74:	71001c1f 	cmp	w0, #0x7
  400a78:	54fffccd 	b.le	400a10 <eight_queen+0xcc>
  400a7c:	52800140 	mov	w0, #0xa                   	// #10
  400a80:	97fffec0 	bl	400580 <putchar@plt>
  400a84:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400a88:	91011000 	add	x0, x0, #0x44
  400a8c:	b9400000 	ldr	w0, [x0]
  400a90:	11000401 	add	w1, w0, #0x1
  400a94:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400a98:	91011000 	add	x0, x0, #0x44
  400a9c:	b9000001 	str	w1, [x0]
  400aa0:	1400003d 	b	400b94 <eight_queen+0x250>
  400aa4:	b9012bbf 	str	wzr, [x29, #296]
  400aa8:	14000037 	b	400b84 <eight_queen+0x240>
  400aac:	b9401fa0 	ldr	w0, [x29, #28]
  400ab0:	f9400ba2 	ldr	x2, [x29, #16]
  400ab4:	b9412ba1 	ldr	w1, [x29, #296]
  400ab8:	97fffef5 	bl	40068c <not_danger>
  400abc:	7100001f 	cmp	w0, #0x0
  400ac0:	540005c0 	b.eq	400b78 <eight_queen+0x234>  // b.none
  400ac4:	b9012fbf 	str	wzr, [x29, #300]
  400ac8:	1400000d 	b	400afc <eight_queen+0x1b8>
  400acc:	b9401fa0 	ldr	w0, [x29, #28]
  400ad0:	93407c00 	sxtw	x0, w0
  400ad4:	d37df001 	lsl	x1, x0, #3
  400ad8:	b9812fa0 	ldrsw	x0, [x29, #300]
  400adc:	8b000020 	add	x0, x1, x0
  400ae0:	d37ef400 	lsl	x0, x0, #2
  400ae4:	9100a3a1 	add	x1, x29, #0x28
  400ae8:	8b000020 	add	x0, x1, x0
  400aec:	b900001f 	str	wzr, [x0]
  400af0:	b9412fa0 	ldr	w0, [x29, #300]
  400af4:	11000400 	add	w0, w0, #0x1
  400af8:	b9012fa0 	str	w0, [x29, #300]
  400afc:	b9412fa0 	ldr	w0, [x29, #300]
  400b00:	71001c1f 	cmp	w0, #0x7
  400b04:	54fffe4d 	b.le	400acc <eight_queen+0x188>
  400b08:	b9401fa0 	ldr	w0, [x29, #28]
  400b0c:	93407c00 	sxtw	x0, w0
  400b10:	d37df001 	lsl	x1, x0, #3
  400b14:	b9812ba0 	ldrsw	x0, [x29, #296]
  400b18:	8b000020 	add	x0, x1, x0
  400b1c:	d37ef400 	lsl	x0, x0, #2
  400b20:	9100a3a1 	add	x1, x29, #0x28
  400b24:	8b000020 	add	x0, x1, x0
  400b28:	52800021 	mov	w1, #0x1                   	// #1
  400b2c:	b9000001 	str	w1, [x0]
  400b30:	b9401fa1 	ldr	w1, [x29, #28]
  400b34:	90000000 	adrp	x0, 400000 <_init-0x4f8>
  400b38:	91336000 	add	x0, x0, #0xcd8
  400b3c:	b9412ba2 	ldr	w2, [x29, #296]
  400b40:	97fffe8c 	bl	400570 <printf@plt>
  400b44:	b9401fa0 	ldr	w0, [x29, #28]
  400b48:	11000400 	add	w0, w0, #0x1
  400b4c:	9100a3a1 	add	x1, x29, #0x28
  400b50:	aa0103e2 	mov	x2, x1
  400b54:	b9401ba1 	ldr	w1, [x29, #24]
  400b58:	97ffff7b 	bl	400944 <eight_queen>
  400b5c:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400b60:	91012000 	add	x0, x0, #0x48
  400b64:	b9400000 	ldr	w0, [x0]
  400b68:	11000401 	add	w1, w0, #0x1
  400b6c:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400b70:	91012000 	add	x0, x0, #0x48
  400b74:	b9000001 	str	w1, [x0]
  400b78:	b9412ba0 	ldr	w0, [x29, #296]
  400b7c:	11000400 	add	w0, w0, #0x1
  400b80:	b9012ba0 	str	w0, [x29, #296]
  400b84:	b9412ba1 	ldr	w1, [x29, #296]
  400b88:	b9401ba0 	ldr	w0, [x29, #24]
  400b8c:	6b00003f 	cmp	w1, w0
  400b90:	54fff8eb 	b.lt	400aac <eight_queen+0x168>  // b.tstop
  400b94:	b9401fa1 	ldr	w1, [x29, #28]
  400b98:	910073a2 	add	x2, x29, #0x1c
  400b9c:	90000000 	adrp	x0, 400000 <_init-0x4f8>
  400ba0:	9133c000 	add	x0, x0, #0xcf0
  400ba4:	97fffe73 	bl	400570 <printf@plt>
  400ba8:	d503201f 	nop
  400bac:	a8d37bfd 	ldp	x29, x30, [sp], #304
  400bb0:	d65f03c0 	ret

0000000000400bb4 <main>:
  400bb4:	a9af7bfd 	stp	x29, x30, [sp, #-272]!
  400bb8:	910003fd 	mov	x29, sp
  400bbc:	910043a0 	add	x0, x29, #0x10
  400bc0:	d2802001 	mov	x1, #0x100                 	// #256
  400bc4:	aa0103e2 	mov	x2, x1
  400bc8:	52800001 	mov	w1, #0x0                   	// #0
  400bcc:	97fffe5d 	bl	400540 <memset@plt>
  400bd0:	910043a0 	add	x0, x29, #0x10
  400bd4:	aa0003e2 	mov	x2, x0
  400bd8:	52800101 	mov	w1, #0x8                   	// #8
  400bdc:	52800000 	mov	w0, #0x0                   	// #0
  400be0:	97ffff59 	bl	400944 <eight_queen>
  400be4:	52800000 	mov	w0, #0x0                   	// #0
  400be8:	a8d17bfd 	ldp	x29, x30, [sp], #272
  400bec:	d65f03c0 	ret

0000000000400bf0 <__libc_csu_init>:
  400bf0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400bf4:	910003fd 	mov	x29, sp
  400bf8:	a901d7f4 	stp	x20, x21, [sp, #24]
  400bfc:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf2f0>
  400c00:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf2f0>
  400c04:	91374294 	add	x20, x20, #0xdd0
  400c08:	913722b5 	add	x21, x21, #0xdc8
  400c0c:	a902dff6 	stp	x22, x23, [sp, #40]
  400c10:	cb150294 	sub	x20, x20, x21
  400c14:	f9001ff8 	str	x24, [sp, #56]
  400c18:	2a0003f6 	mov	w22, w0
  400c1c:	aa0103f7 	mov	x23, x1
  400c20:	9343fe94 	asr	x20, x20, #3
  400c24:	aa0203f8 	mov	x24, x2
  400c28:	97fffe34 	bl	4004f8 <_init>
  400c2c:	b4000194 	cbz	x20, 400c5c <__libc_csu_init+0x6c>
  400c30:	f9000bb3 	str	x19, [x29, #16]
  400c34:	d2800013 	mov	x19, #0x0                   	// #0
  400c38:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c3c:	aa1803e2 	mov	x2, x24
  400c40:	aa1703e1 	mov	x1, x23
  400c44:	2a1603e0 	mov	w0, w22
  400c48:	91000673 	add	x19, x19, #0x1
  400c4c:	d63f0060 	blr	x3
  400c50:	eb13029f 	cmp	x20, x19
  400c54:	54ffff21 	b.ne	400c38 <__libc_csu_init+0x48>  // b.any
  400c58:	f9400bb3 	ldr	x19, [x29, #16]
  400c5c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400c60:	a942dff6 	ldp	x22, x23, [sp, #40]
  400c64:	f9401ff8 	ldr	x24, [sp, #56]
  400c68:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c6c:	d65f03c0 	ret

0000000000400c70 <__libc_csu_fini>:
  400c70:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c74 <_fini>:
  400c74:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c78:	910003fd 	mov	x29, sp
  400c7c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c80:	d65f03c0 	ret
